Various Group III-V compounds are being investigated for use in high-power electronics applications. These compounds include “Group III-nitrides” such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlInGaN). These compounds are often fabricated by epitaxial growth on substrates such as silicon, sapphire, and silicon carbide. The use of silicon substrates is often preferred due to its lower fabrication costs. Also, silicon substrates are suitable for monolithic integration with other silicon-based devices, such as CMOS and BiCMOS devices.
One problem is that epitaxial growth of Group III-nitrides on silicon <111> substrates often results in large lattice and thermal coefficient mismatches. Lattice mismatch can cause concave bending of the epitaxial layers and substrates, along with large threading dislocation density formations. When the thickness of an epitaxial layer exceeds a critical value, cracking and delimination can also occur. High thermal mismatch between the epitaxial layers and substrates can create tensile stress during cooling, which can cause additional cracking and delimination. As an example, gallium nitride films grown by Metal-Organic Chemical Vapor Deposition (MOCVD) are often subject to about 1 GPa tensile stress per micron of gallium nitride.
The cracking and delimination that occur can vary based on the diameter of a silicon substrate, a thickness of the silicon substrate, and a thickness of the epitaxial layer. For smaller-diameter silicon substrates (such as three-inch and four-inch diameter wafers), the maximum epitaxial layer thickness that can be achieved without cracks is often around 2.5 μm-3 μm. For larger-diameter silicon substrates (such as six-inch diameter wafers or larger), the maximum epitaxial layer thickness that can be achieved without cracks is typically 1 μm-2 μm for substrate thicknesses of about 650 μm-700 μm. Power devices with high breakdown voltages (such as more than 1,000V) often require epitaxial layer thicknesses in excess of 3.5 μm, which typically cannot be achieved with larger silicon substrates using current methods.